3BHB002916R0001 UFC721AE

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UFC721AE 3BHB002916R0001 ABB控制板驱动板主板

型号：3BHB002916R0001 UFC721AE

品牌：ABB

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                                                   产品详情资料：

3BHB002916R0001 UFC721AE

在步骤5中，传输编程后，设置DGCS中的GO位。如果由于PCI_CSR中的BM位未设置为启用PCI总线主控权，或者源和目标起始地址未对齐，DMA编程不正确，则将断言P_ERR。否则，将设置ACT位，然后DMA将开始传输数据，与PCI目标和中断通道共享VMEbus的所有权，与VMEbus从属通道共享PCI总线的所有权。在步骤6中，等待DMA传输的终止。DMA将继续传输，直到：?完成所有传输，?使用STOP_REQ位提前终止，或?在PCI总线或VMEbus上遇到错误。这些条件中的每一个都将导致ACT位清零，并在DGCS寄存器中设置相应的状态位。如果在步骤1中启用，也将生成中断。一旦软件设置了GO位，软件就可以通过等待中断生成或轮询状态位来监控DMA完成。建议还启动后台计时器以使传输超时。这将确保DMA没有被繁忙的VMEbus或其他此类系统问题挂断。

                                                  产品英文详情料:

In Step 5, with the transfer programmed, the GO bit in DGCS must be set. If the DMA has been improperly programmed, either because the BM bit in the PCI_CSR has not been set to enable PCI bus mastership, or the source and destination start addresses are not aligned, then P_ERR will be asserted. Otherwise, the ACT bit will be set, and the DMA will then start transferring data, sharing ownership of the VMEbus with the PCI Target and Interrupt channels and the PCI bus with the VMEbus Slave Channel. In Step 6, one waits for termination of the DMA transfers. The DMA will continue with the transfers until it: ? completes all transfers, ? is terminated early with the STOP_REQ bit, or ? encounters an error on the PCI bus or VMEbus. Each of these conditions will cause the ACT bit to clear, and a corresponding status bit to be set in the DGCS register. If enabled in Step 1, an interrupt will also be generated. Once the software has set the GO bit, the software can monitor for DMA completion by either waiting for generation of an interrupt, or by polling the status bits. It is recommended that a background timer also be initiated to time-out the transfer. This will ensure that the DMA has not been hung up by a busy VMEbus, or other such system issues.

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